Metal gates of transistors having reduced resistivity

ABSTRACT

A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No.16/191,908, entitled “Metal Gates of Transistors Having ReducedResistivity,” and filed Nov. 15, 2018, which is a continuation of U.S.patent application Ser. No. 15/613,485, entitled “Metal Gates ofTransistors Having Reduced Resistivity,” and filed Jun. 5, 2017, nowU.S. patent. No. 10,141,225 issued Nov. 27, 2018, which claims thebenefit of U.S. Provisional Application No. 62/491,823, filed Apr. 28,2017, and entitled “Metal Gates of Transistors Having ReducedResistivity,” which applications are hereby incorporated herein byreference.

BACKGROUND

Metal-Oxide-Semiconductor (MOS) devices are basic building elements inintegrated circuits. An existing MOS device typically has a gateelectrode formed of polysilicon doped with p-type or n-type impurities,using doping operations such as ion implantation or thermal diffusion.The work function of the gate electrode may be adjusted to the band-edgeof silicon. For an n-type Metal-Oxide-Semiconductor (NMOS) device, thework function may be adjusted to close to the conduction band ofsilicon. For a P-type Metal-Oxide-Semiconductor (PMOS) device, the workfunction may be adjusted to close to the valence band of silicon.Adjusting the work function of the polysilicon gate electrode can beachieved by selecting appropriate impurities.

MOS devices with polysilicon gate electrodes exhibit carrier depletioneffect, which is also known as a poly depletion effect. The polydepletion effect occurs when the applied electrical fields sweep awaycarriers from gate regions close to gate dielectrics, forming depletionlayers. In an n-doped polysilicon layer, the depletion layer includesionized non-mobile donor sites, wherein in a p-doped polysilicon layer,the depletion layer includes ionized non-mobile acceptor sites. Thedepletion effect results in an increase in the effective gate dielectricthickness, making it more difficult for an inversion layer to be createdat the surface of the semiconductor.

The poly depletion problem may be solved by forming metal gateelectrodes, wherein the metallic gates used in NMOS devices and PMOSdevices may also have band-edge work functions. Accordingly, theresulting metal gates include a plurality of layers to meet therequirements of the NMOS devices and PMOS devices.

The formation of metal gates typically involves depositing metal layersand then performing Chemical Mechanical Polish (CMP) to remove excessportions of the metal layers. The remaining portions of the metal layersform metal gates. The metal gates are then recessed. The metal gates mayinclude tungsten. However, tungsten does not have good adhesion tounderlying layers. Accordingly, a tungsten nucleation layer is formed,followed by the deposition of an additional tungsten layer. The tungstennucleation layer has improved adhesion to its underlying layer. Theresistivity of the tungsten nucleation layer, however, is much higherthan the overlying deposited tungsten. Accordingly, when the MOS devicesare scaled down, and the widths of the metal gates are very small, theresistivity of the tungsten nucleation layer significantly impacts theperformance of the resulting transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1 through 18 illustrate the cross-sectional views and perspectiveviews of intermediate stages in the formation of Fin Field-EffectTransistors (FinFETs) in accordance with some embodiments.

FIG. 19 illustrates a cross-sectional view of a FinFET with actualprofile illustrated in accordance with some embodiments.

FIG. 20 illustrates a flow chart of a process for forming a FinFET inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,”“lower,” “overlying,” “upper” and the like, may be used herein for easeof description to describe one element or feature's relationship toanother element(s) or feature(s) as illustrated in the figures. Thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

Transistor and the methods of forming the same are provided inaccordance with various exemplary embodiments. The intermediate stagesof forming the transistors are illustrated in accordance with someembodiments. Some variations of some embodiments are discussed.Throughout the various views and illustrative embodiments, likereference numbers are used to designate like elements. In theillustrated exemplary embodiments, the formation of Fin Field-EffectTransistor (FinFETs) is used as an example to explain the concepts ofthe present disclosure. Planar transistors may also adopt the concept ofthe present disclosure.

FIGS. 1 through 18 illustrate the cross-sectional views and perspectiveviews of intermediate stages in the formation of FinFETs in accordancewith some embodiments of the present disclosure. The steps shown inFIGS. 1 through 18 are also reflected schematically in the process flowshown in FIG. 20.

FIG. 1 illustrates a perspective view of an initial structure. Theinitial structure includes wafer 10, which further includes substrate20. Substrate 20 may be a semiconductor substrate, which may be asilicon substrate, a silicon germanium substrate, or a substrate formedof other semiconductor materials. Substrate 20 may be doped with ap-type or an n-type impurity. Isolation regions 22 such as ShallowTrench Isolation (STI) regions may be formed to extend from a topsurface of substrate 20 into substrate 20, wherein the top surface ofsubstrate 20 is a major surface 10A of wafer 10. The portions ofsubstrate 20 between neighboring STI regions 22 are referred to assemiconductor strips 24. The top surfaces of semiconductor strips 24 andthe top surfaces of STI regions 22 may be substantially level with eachother in accordance with some exemplary embodiments.

STI regions 22 may include a liner oxide (not shown). The liner oxidemay be formed of a thermal oxide formed through a thermal oxidation of asurface layer of substrate 20. The liner oxide may also be a depositedsilicon oxide layer formed using, for example, Atomic Layer Deposition(ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), orChemical Vapor Deposition (CVD). STI regions 22 may also include adielectric material over the liner oxide, wherein the dielectricmaterial may be formed of Flowable Chemical Vapor Deposition (FCVD),spin-on, or the like.

Referring to FIG. 2, STI regions 22 are recessed, so that the topportions of semiconductor strips 24 protrude higher than the topsurfaces of STI regions 22 to form protruding fins 24′. The etching maybe performed using a dry etching process, wherein HF₃ and NH₃ are usedas the etching gases. During the etching process, plasma may begenerated. Argon may also be included. In accordance with alternativeembodiments of the present disclosure, the recessing of STI regions 22is performed using a wet etch process. The etching chemical may includediluted HF, for example.

Referring to FIG. 3, dummy gate stack 30 is formed on the top surfacesand the sidewalls of protruding fins 24′. Dummy gate stack 30 mayinclude dummy gate dielectric 32 and dummy gate electrode 34 over dummygate dielectric 32. Dummy gate electrode 34 may be formed, for example,using polysilicon, and other materials may also be used. Dummy gatestack 30 may also include one (or a plurality of) hard mask layer 36over dummy gate electrode 34. Hard mask layer 36 may be formed ofsilicon nitride, silicon carbo-nitride, or the like. Dummy gate stack 30may cross over a single one or a plurality of protruding fins 24′ and/orSTI regions 22. Dummy gate stack 30 may also have a lengthwise directionperpendicular to the lengthwise direction of protruding fins 24′.

Next, gate spacers 38 are formed on the sidewalls of dummy gate stack30. In accordance with some embodiments of the present disclosure, gatespacers 38 are formed of a dielectric material such as siliconcarbon-oxyitride (SiCN), silicon nitride, or the like, and may have asingle-layer structure or a multi-layer structure including a pluralityof dielectric layers.

An etching step (referred to as source/drain recessing hereinafter) isthen performed to etch the portions of protruding fins 24′ that are notcovered by dummy gate stack 30 and gate spacers 38, resulting in thestructure shown in FIG. 4. The recessing may be anisotropic, and hencethe portions of fins 24′ directly underlying dummy gate stack 30 andgate spacers 38 are protected, and are not etched. The top surfaces 24Aof the recessed semiconductor strips 24 may be lower than the topsurfaces 22A of STI regions 22 in accordance with some embodiments.Recesses 40 are accordingly formed between STI regions 22. Recesses 40are located on opposite sides of dummy gate stack 30.

Next, epitaxy regions (source/drain regions) are formed by selectivelygrowing a semiconductor material in recesses 40, resulting in thestructure in FIG. 5. In accordance with some exemplary embodiments,epitaxy regions 42 include silicon germanium or silicon. Depending onwhether the resulting FinFET is a p-type FinFET or an n-type FinFET, ap-type or an n-type impurity may be in-situ doped with the proceeding ofthe epitaxy. For example, when the resulting FinFET is a p-type FinFET,silicon germanium boron (SiGeB) may be grown. Conversely, when theresulting FinFET is an n-type FinFET, silicon phosphorous (SiP) orsilicon carbon phosphorous (SiCP) may be grown. In accordance withalternative embodiments of the present disclosure, epitaxy regions 42 isformed of a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs,InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, ormulti-layers thereof. After recesses 40 are filled with epitaxy regions42, the further epitaxial growth of epitaxy regions 42 causes epitaxyregions 42 to expand horizontally, and facets may be formed.

After the epitaxy step, epitaxy regions 42 may be further implanted witha p-type or an n-type impurity to form source and drain regions, whichare also denoted using reference numeral 42. In accordance withalternative embodiments of the present disclosure, the implantation stepis skipped when epitaxy regions 42 are in-situ doped with the p-type orn-type impurity during the epitaxy. Epitaxy regions 42 include lowerportions 42A that are formed in STI regions 22, and upper portions 42Bthat are formed over the top surfaces 22A of STI regions 22. Lowerportions 42A, whose sidewalls are shaped by the shapes of recesses 40(FIG. 4), may have (substantially) straight edges, which may also besubstantial vertical edges that are substantial perpendicular to themajor surfaces (such as the bottom surface) of substrate 20.

FIG. 6A illustrates a perspective view of the structure with Inter-LayerDielectric (ILD) 46 being formed. In accordance with some embodiments ofthe present disclosure, a buffer oxide layer (not shown) and ContactEtch Stop Layer (CESL) 47 are formed on source and drain regions 42before the formation of ILD 46. The buffer oxide layer may be formed ofsilicon oxide, and CESL 47 may be formed of silicon nitride, siliconcarbo-nitride, or the like. The buffer oxide layer and CESL 47 may beformed using a conformal deposition method such as ALD, for example. ILD46 may include a dielectric material formed using, for example, FCVD,spin-on coating, CVD, or other deposition methods. ILD 46 may also beformed of Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG),Boron-Doped Phospho-Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate(TEOS) oxide, or the like. A planarization such as Chemical MechanicalPolish (CMP) or mechanical grinding may be performed to level the topsurfaces of ILD 46, dummy gate stack 30, and gate spacers 38 with eachother.

A cross-sectional view of the structure shown in FIG. 6A is illustratedin FIG. 6B, wherein the cross-sectional view is obtained from thevertical plane containing line A-A in FIG. 6A. Next, the dummy gatestack 30 including hard mask layer 36, dummy gate electrode 34 and dummygate dielectric 32 are replaced with a metal gate and a replacement gatedielectric. The cross-sectional views shown in FIGS. 7 through 18 areobtained from the same vertical plane containing line A-A in FIG. 6A. InFIGS. 7 through 18, the level 22A of the top surfaces of STI regions 22are illustrated, and semiconductor fins 24′ are over level 22A.

Hard mask layer 36, dummy gate electrode 34, and dummy gate dielectric32 as shown in FIGS. 6A and 6B are removed, resulting in opening 48 asshown in FIG. 7 to be formed. The respective step is illustrated as step202 in the process flow shown in FIG. 20. The top surfaces and thesidewalls of protruding fins 24′ are exposed to opening 48.

FIG. 7 further illustrates the formation of gate spacers 50 inaccordance with some embodiments. In accordance with alternativeembodiments, gate spacers 50 are not formed. To form gate spacers 50, ablanket gate spacer layer may be formed, for example, using a depositionmethod such as ALD or CVD. The blanket gate spacer layer is conformal.In accordance with some embodiments of the present disclosure, the gatespacer layer is formed of silicon nitride (SiN), SiC, SiON, or anotherdielectric material, which may be the same or different from either oneof the materials of gate spacers 38 and the materials of CESL 47 and ILD46. Gate spacers 50 separate the subsequently formed metal gate fartheraway from source/drain regions 42, and the possibility of leakage andelectrical shorting between them are reduced.

Next, referring to FIG. 8, gate dielectric 52 formed, which extends intoopening 48. The respective step is illustrated as step 204 in theprocess flow shown in FIG. 20. In accordance with some embodiments ofthe present disclosure, gate dielectric 52 includes Interfacial Layer(IL) 54 as its lower part. IL 54 is formed on the exposed surfaces ofprotruding fins 24′. IL 54 may include an oxide layer such as a siliconoxide layer, which is formed through the thermal oxidation of protrudingfins 24′, a chemical oxidation process, or a deposition process. Gatedielectric 52 may also include high-k dielectric layer 56 formed over IL54. High-k dielectric layer 56 includes a high-k dielectric materialsuch as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide,or the like. The dielectric constant (k-value) of the high-k dielectricmaterial is higher than 3.9, and may be higher than about 7.0. High-kdielectric layer 56 is overlying, and may contact, IL 54. High-kdielectric layer 56 is formed as a conformal layer, and extends on thesidewalls of protruding fins 24′ and the top surface and the sidewallsof gate spacers 38/50. In accordance with some embodiments of thepresent disclosure, high-k dielectric layer 56 is formed using ALD orCVD.

Referring further to FIG. 8, stacked layers 58 is deposited. Therespective step is illustrated as step 206 in the process flow shown inFIG. 20. The sub-layers in stacked layers 58 are not shown separately,while in reality, the sub-layers are distinguishable since thesub-layers are formed of different materials and/or have differentpercentages of elements. The deposition may be performed using aconformal deposition method such as ALD or CVD, so that the thickness T1of the vertical portions and thickness T2 of the horizontal portions ofstacked layers 58 (and each of sub-layers) have thicknessessubstantially equal to each other. Stacked layers 58 extend into opening48, and include some portions over ILD 46.

Stacked layers 58 may include a diffusion barrier layer and one or morework function layer over the diffusion barrier layer. The diffusionbarrier layer may be formed of titanium nitride, which may (or may not)be doped with silicon. Titanium nitride, when doped with silicon, isalso sometimes referred to as titanium silicon nitride (Ti-Si-N, orTSN). Titanium nitride or titanium silicon nitride is a conductivematerial. The work function layer determines the work function of thegate electrode, and includes at least one layer, or a plurality oflayers formed of different materials. The specific material of the workfunction layer may be selected according to whether the respectiveFinFET is an n-type FinFET or a p-type FinFET. For example, when theFinFET is an n-type FinFET, the work function layer may include a TaNlayer and a titanium aluminum (TiAl) layer over the TaN layer. When theFinFET is a p-type FinFET, the work function layer may include a TaNlayer, a TiN layer over the TaN layer, and a TiAl layer over the TiNlayer. After the deposition of stacked layers 58, barrier layer 60,which may be another TiN layer, is formed. TiN layer 60 may be formedusing CVD, and may act as a blocking layer. The respective step is alsoillustrated as step 206 in the process flow shown in FIG. 20. TiN layer60 may be free from silicon in accordance with some embodiments.

Next, metal-containing material 62 is deposited, which has a bottomsurface in physical contact with the top surface of TiN layer 60. Therespective step is illustrated as step 208 in the process flow shown inFIG. 20. The formation of metal-containing material 62 may be achievedthrough CVD, ALD, or PVD. In accordance with some embodiments of thepresent disclosure, Physical Vapor Deposition (PVD) is used, which isperformed using a cobalt target disposed over the respective wafer 10.In addition, precursors are also introduced during the PVD. Accordingly,the deposition includes both the PVD and the CVD. In accordance withsome embodiments, the precursors for depositing metal-containingmaterial 62 include a cobalt-containing precursor, a silicon-containingprecursor, and possibly other gases. For example, the precursors forforming metal-containing material 62 may include tetraethoxysilane(TEOS), SiHCl₃, and a cobalt-containing precursor such as di-cobaltoctacarbonyl, cobalt nitrosyl complexes, or β-diketonates of cobalt (II)and cobalt (III), and the like.

In accordance with some embodiments, metal-containing material 62includes layer 62A and layer 62B over layer 62A. In accordance with someembodiments, layer 62A is a cobalt silicide (Co_(x)Si_(y), with x and ybeing atomic percentages and having values between 0 and 1.0) layer.Layer 62B is a cobalt layer free from, or substantially free from (forexample, with an atomic percentage lower than about 1 percent), siliconor other elements. With both layers 62A and 62B being cobalt-containinglayers, the manufacturing cost may be reduced. For example, the samesilicon-containing precursor and cobalt-containing precursor (andpossibly an additional Co target) may be used for depositing both layer62A and 62B. In accordance with an exemplary deposition process, whenlayer 62A (Co_(x)Si_(y)) is deposited, the temperature of wafer 10 maybe in the range between about 85° C. and about 120° C. After thedeposition of layer 62A is concluded, the temperature of wafer 10 islowered, for example, to about 25° C., and with the same precursors(with or without using the additional Co target), cobalt layer 62B,which is free or substantially free from silicon, is formed. Inaccordance with some embodiments, the transition from the deposition oflayer 62A to the deposition of layer 62B is achieved by lowering thetemperature of wafer 10, while maintaining other process conditions(such as flow rates of the precursors, the partial pressures, thepowers, etc.) unchanged. The formation of metal-containing material 62may also be achieved by gradually reducing the temperature of wafer 10,so that layer 62A has a gradually reduced silicon content, with upperportions of layer 62A having less silicon than the respective lowerportions. The gradual reduction of temperature may be continuous. Thegradual reduction of temperature may also be through abrupt steps, whichmeans the temperature abruptly drops to a lower step, and stay unchangedfor a while before dropping to another lower stage. The gradualtransition is continued until respective formed layer is free orsubstantially free from silicon, at which time layer 62 starts to form.The temperature may then be stable when the resulting layer is a cobaltlayer. Accordingly, the entire layer 62B may be a cobalt layer free orsubstantially free from silicon and other elements, while layer 62A hasgradually (abruptly or continuously) reduced silicon percentage.

In accordance with alternative embodiments, lower layer 62A is a cobaltlayer, and upper layer 62B is a cobalt silicide layer. The formationprocess may be reversed than discussed above to form layers 62A and 62B.

In accordance with some embodiments, layer 62A is formed of a metalsilicide (using a metal other than cobalt), which may be Ti_(x)Si_(y),Ni_(x)Si_(y), W_(x)Si_(y), Mo_(x)Si_(y), Ta_(x)Si_(y), and layer 62B isa cobalt layer free or substantially free from silicon and otherelements.

In accordance with some embodiments, the entire layer 62 is formed of ahomogenous material, which may be cobalt (free or substantially freefrom silicon and other elements) or a metal silicide such asTi_(x)Si_(y), Ni_(x)Si_(y), W_(x)Si_(y), Mo_(x)Si_(y), or Ta_(x)Si_(y).The entire layer 62 has a uniform resistivity. When formed of thesilicide layer, the entire layer 62 may have constant percentages x andy, and has the uniform resistivity, or may have gradually changed (suchas gradually reduced or gradually increased) percentages x and y frombottom to top. The formation process may thus have constant processconditions (such as temperature, pressure, flow rate, or the like)throughout the formation of entire layer 62.

Next, a planarization such as a Chemical Mechanical Polish (CMP) ormechanical grinding is performed, so that the portions of layers 56, 58,60, and 62 over ILD 46 are removed. The respective step is illustratedas step 210 in the process flow shown in FIG. 20. Next, as shown in FIG.9, layers 56, 58, 60, and 62 are etched back, forming recess 63. Therespective step is illustrated as step 212 in the process flow shown inFIG. 20. The remaining portion of layers 54, 56, 58, 60, and 62 arereferred to as replacement gate stack 64 hereinafter.

Hard mask 66 is formed over replacement gate stack 64, as shown in FIG.10. The respective step is also illustrated as step 212 in the processflow shown in FIG. 20. In accordance with some embodiments of thepresent disclosure, the formation of hard mask 66 includes a depositionstep to form a blanket dielectric material, and a planarization step toremove the excess dielectric material over gate spacers 38 and ILD 46.Hard mask 66 may be formed of silicon nitride, for example.

FIGS. 11 through 14 illustrate the formation of lower source/draincontact plugs. Referring to FIG. 11, dielectric layer 67 is formed overthe structure shown in FIG. 10, followed by the application of apatterned photo resist (not shown). Next, dielectric layer 67, ILD 46,and CESL 47 are etched to form contact openings 68. The respective stepis illustrated as step 214 in the process flow shown in FIG. 20.

Further referring to FIG. 11, metal layer 72 (such as a titanium layeror a tantalum layer) is deposited, for example, using PVD. Barrier layer74, which may be a metal nitride layer such as a titanium nitride layeror a tantalum nitride layer is then formed over metal layer 72. Therespective step is illustrated as step 216 in the process flow shown inFIG. 20. Barrier layer 74 may be formed of using CVD. Layers 72 and 74are both conformal, and extend into openings 68.

An anneal is then performed to form source/drain silicide regions 76, asshown in FIG. 12. The respective step is illustrated as step 218 in theprocess flow shown in FIG. 20. The anneal may be performed through RapidThermal Anneal (RTA), furnace anneal, or the like. Accordingly, thebottom portion of metal layer 72 reacts with source/drain region 42 toform silicide regions 76. The sidewall portions of metal layer 72 remainafter the silicidation process. In accordance with some embodiments ofthe present disclosure, the top surface of silicide regions 76 are incontact with the bottom surface of barrier layer 74.

Next, as shown in FIG. 13, metal-containing layer 78 is deposited overand in contact with barrier layer 74. The respective step is illustratedas step 220 in the process flow shown in FIG. 20. Metal-containing layer78 may be formed a material selected from the same group of candidatematerials of metal-containing material 62. Furthermore, the formationmethod, the material, and the structure of metal-containing layer 78 mayalso be selected from the candidate formation methods, the candidatematerials, and the candidate structures of metal-containing material 62.For example, metal-containing layer 78 may be a homogenous cobalt layeror a homogenous metal silicide layer, or may include a lower layer 78Aand upper layer 78B, wherein the formation methods, the materials, andmaterials of layers 78A and 78B may be found referring to theabove-discussed layers 62A and 62B, respectively, in any combination.

A planarization such as a CMP is then performed to remove the portionsof layers 72 and 74 over layer 67. The respective step is illustrated asstep 222 in the process flow shown in FIG. 20. The resulting structureis shown in FIG. 14, which illustrate source/drain contact plugs 79.Each of source/drain contact plugs 79 includes metal-containing layer78, barrier layer 74, and metal layer 72.

FIGS. 15 through 17 illustrate the formation of a gate contact plug. Therespective step is illustrated as step 224 in the process flow shown inFIG. 20. Referring to FIG. 15, a photo lithography process is performedusing a lithography mask (not shown) to etch-through dielectric layer67. Hard mask 66 (FIG. 14) is then removed, forming opening 80. Inaccordance with some embodiments of the present disclosure, theformation of opening 80 includes an anisotropic etching to etch-throughdielectric layer 67, and an isotropic etching (dry or wet) or ananisotropic etch to remove hard mask 66. The sidewalls of gate spacers50 (if any) are thus exposed. In the embodiments in which gate spacers50 are not formed, the sidewalls of gate spacers 38 are exposed toopening 80. The etchant for etching dielectric layer 67 and hard mask 66are selected, so that gate spacers 50 and 38 are substantially notetched. In accordance with alternative embodiments of the presentdisclosure, opening 80 is narrower than hard mask 66, and hence someedge portions of hard mask 66 are left after the etching.

Referring to FIG. 16, barrier layer 82 and metal-containing material 84are deposited. Barrier layer 82 may be formed of titanium nitride ortantalum nitride. The material, the structure, and the formation methodof metal-containing material 84 may be selected from the candidatematerials, the candidate structures, and the candidate formationmethods, respectively, of metal-containing material 62, and hence thedetails are not repeated herein, and may be found referring to thediscussion of metal-containing material 62. Accordingly, similar tometal-containing material 62, metal-containing material 84 may also beformed of cobalt, a metal silicide, or composite layers thereof. In asubsequent step, a planarization such as a CMP is performed. Theplanarization may be performed until all of layer 67 is removed, and ILD46 is exposed. Accordingly, layer 67 acts as a sacrificial layer. Theresulting structure is shown in FIG. 17, which illustrates contact plug86 formed of the remaining portions of layers 82 and 84. FinFET 300 isthus formed.

FIG. 18 illustrates the formation of etch stop layer 88, ILD 90, andsource/drain contact plugs (vias) 92 in etch stop layer 88 and ILD 90.Etch stop layer 88 may be formed of silicon carbide, silicon oxynitride,silicon carbo-nitride, or the like, and may be formed using a depositionmethod such as CVD. ILD 90 may include a material selected from PSG,BSG, BPSG, Fuorine-doped Silicon Glass (FSG), TEOS oxide, or othernon-porous low-k dielectric materials. ILD 90 may be formed using spincoating, Flowable Chemical Vapor Deposition (FCVD), or the like, orformed using a deposition method such as Plasma Enhanced Chemical VaporDeposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), orthe like.

ILD 90 and etch stop layer 88 are etched to form openings (occupied byvias 92). The etching may be performed using, for example, Reactive IonEtch (RIE). In a subsequent step, vias 92 are formed. In accordance withsome embodiments, vias 92 include barrier layer 94 and metal-containingmaterial 96 over barrier layer 94. In accordance with some embodimentsof the present disclosure, the formation of vias 92 include etchinglayers 88 and 90 to form contact openings, forming a blanket barrierlayer and a metal-containing material over the blanket barrier layer,and performing a planarization to remove excess portions of the blanketbarrier layer and the metal-containing material. Barrier layer 94 may beformed of a metal nitride such as titanium nitride or tantalum nitride.The material, the structure, and the formation methods ofmetal-containing material 96 may be selected from the candidatematerials, the candidate structures, and the candidate formationmethods, respectively, of metal-containing material 62, and hence thedetails are not repeated herein.

Vias 92 have sidewalls with tilting angle α in the range between about80 degrees and about 90 degrees. Vias 92 also have top widths W_(top)greater than the respective bottom width W_(bottom). For example, ratioW_(top)/W_(bottom) may be in the range between about 1.2 and about 1.5.Such profile is good for gap filling.

FIG. 19 illustrates a cross-sectional view of a FinFET in accordancewith some embodiments. In accordance with some embodiments of thepresent disclosure, as shown in FIG. 19, the sidewalls of contact plugs92 have substantially straight and slanted lower portions, and curvedupper portions, and line 93 is drawn to show the transitioning levelbetween the upper portion and the lower portion. The upper portions ofthe sidewalls may have substantial abrupt change of slope comparing tothe respective lower portions. The height of contact plug 92 is markedas H1. The height of the top portion of contact plug 92 is marked as H2.The top width and the bottom width are marked as W_(top) and W_(bottom),respectively. Width W_(bottom) is measured at 95% of the depth H1 ofcontact plug 92. The width of contact plug 92 at the transition point isW_(tran). In accordance with some embodiments of the present disclosure,ratio W_(tran)/W_(bottom) may be between about 1.2 and about 1.5. Theration H2/H1 may be between about 0.1 and about 0.2. Slant angle α maybe between about 80 degrees and about 90 degrees, and may be around 85degrees. Although the dimensions and slant angles of contact plugs 79are not illustrated in detail, contact plugs 79 may have similarprofiles.

The embodiments of the present disclosure have some advantageousfeatures. When etching dielectric layers, polymers may be generated. Inorder to remove the residue polymer formed due to the etching ofdielectric layers, an acidic solution (such as H₂O₂), may be used.Cobalt has good resistance to acid. The acidic solution causes thecorrosion of the exposed metal. If tungsten is used, it is more likelyto be corroded. Cobalt, on the other hand, is more resistant to thecorrosion, and the problem generated by the corrosion of the metal suchas metal gate loss, may be reduced. Cobalt also has a smaller roughnessthan tungsten, making it a better material for forming high-qualityfilms.

In addition, cobalt and metal silicides have low resistivity values thantungsten at very small dimensions due to scattering effect. Also,tungsten doesn't have good adhesion to some barrier materials such asTiN. Accordingly, conventionally, a nucleation tungsten layer wasformed, followed by the deposition of tungsten using CVD. The tungstennucleation layer has a resistivity in the range between about 200μOhm*cm and about 250 μOhm*cm, which is much higher than the resistivity(about 5.7 μOhm*cm) of CVD tungsten. Accordingly, the resistivity of thenucleation tungsten layer significantly degrades the performance of theresulting transistor. Cobalt (or metal silicide), on the other hand, hasa very low resistivity (about 5.8 μOhm*cm for cobalt silicide), and hasgood adhesion to TiN. Accordingly, by adopting cobalt and/or metalsilicide, the adhesion to the underlying barrier layer is good, and theresistivity of the metal gate is low.

In accordance with some embodiments of the present disclosure, a methodincludes forming a transistor, which includes forming a gate dielectricon a semiconductor region, forming a gate electrode over the gatedielectric, and forming a source/drain region extending into thesemiconductor region. The method further includes forming a source/draincontact plug over and electrically coupling to the source/drain region,and forming a gate contact plug over and in contact with the gateelectrode. At least one of the forming the gate electrode, the formingthe source/drain contact plug, and the forming the gate contact plugincludes forming a metal nitride barrier layer, and depositing ametal-containing layer over and in contact with the metal nitridebarrier layer. The metal-containing layer includes at least one of acobalt layer and a metal silicide layer.

In accordance with some embodiments of the present disclosure, a methodincludes forming a transistor, which includes forming a dummy gate stackover a semiconductor region, forming an ILD with the dummy gate stackbeing in the ILD, removing the dummy gate stack to form an opening inthe ILD, forming a replacement gate dielectric extending into theopening, forming a work-function metal layer over the replacement gatedielectric, forming a barrier layer including titanium nitride over thereplacement gate dielectric, and depositing a cobalt-containing layerextending into the opening. The cobalt-containing layer overlies, and isin contact with, the barrier layer. A planarization is performed toremove excess portions of the replacement gate dielectric, thework-function metal layer, the barrier layer, and the cobalt-containinglayer to from a replacement gate stack. A source region and a drainregion are formed on opposite sides of the replacement gate stack.

In accordance with some embodiments of the present disclosure, a deviceincludes gate spacers, a gate dielectric, and a gate electrode. The gateelectrode includes a first metal nitride layer over the gate dielectric,and a work-function metal layer over the first metal nitride layer. Thegate dielectric and the gate electrode extend between the gate spacers.A gate contact plug is over and contacting the gate electrode. Asource/drain region is adjacent to the gate electrode. A source/draincontact plug is over and electrically coupling to the source/drainregion. At least one of the gate electrode, the source/drain contactplug, and the gate contact plug includes a second metal nitride layer,and a metal-containing layer over and contacting the second metalnitride layer. The metal-containing layer includes at least one of acobalt layer and a metal silicide layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. An integrated circuit device comprising: a semiconductor region; a gate dielectric over the semiconductor region; a gate electrode over a bottom portion of the gate dielectric; a gate contact plug over and contacting the gate electrode; a source/drain region adjacent to the gate electrode; a source/drain silicide region over and contacting the source/drain region; and a source/drain contact plug over and contacting the source/drain silicide region, wherein a conductive region selected from the group consisting of the gate electrode, the source/drain contact plug, and the gate contact plug comprises a metal silicide layer.
 2. The integrated circuit device of claim 1, wherein the conductive region further comprises a non-silicide metal layer over the metal silicide layer, and the non-silicide metal layer comprises a same metal as the metal silicide layer.
 3. The integrated circuit device of claim 2, wherein the non-silicide metal layer and the metal silicide layer comprise cobalt.
 4. The integrated circuit device of claim₃, wherein the non-silicide metal layer is free from elements other than cobalt.
 5. The integrated circuit device of claim 1, wherein the conductive region comprises the source/drain contact plug, and the source/drain contact plug comprises a metal nitride layer, and wherein the metal silicide layer and the source/drain silicide region are separated from each other by the metal nitride layer.
 6. The integrated circuit device of claim₅, wherein the metal silicide layer contacts a top surface of the metal nitride layer, and the source/drain silicide region contacts a bottom surface of the metal nitride layer.
 7. The integrated circuit device of claim 1, wherein the conductive region comprises the gate electrode, and the gate electrode further comprises a non-silicide conductive layer over the metal silicide layer.
 8. The integrated circuit device of claim 1, wherein the conductive region comprises the gate contact plug, and the integrated circuit device further comprises: gate spacers on opposing sides of the gate electrode, wherein the gate contact plug extends to a level lower than top surfaces of the gate spacers.
 9. The integrated circuit device of claim 1 further comprising an additional gate contact plug over and contacting the gate contact plug, wherein a sidewall of the additional gate contact plug has a tilt angle in a range between about 80 degrees and about 90 degrees.
 10. An integrated circuit device comprising: a gate electrode; a source/drain region adjacent to the gate electrode; a source/drain silicide region over the source/drain region; and a source/drain contact plug over and electrically coupling to the source/drain region, wherein the source/drain contact plug comprises: a metal nitride layer; and a metal silicide layer over a bottom portion of the metal nitride layer.
 11. The integrated circuit device of claim 10, wherein the source/drain contact plug further comprises a non-silicide metal-containing layer over the metal silicide layer.
 12. The integrated circuit device of claim 11, wherein the non-silicide metal-containing layer is a cobalt layer.
 13. The integrated circuit device of claim 11, wherein the metal silicide layer and the non-silicide metal-containing layer comprise a same metal.
 14. The integrated circuit device of claim 13, wherein an entirety of the non-silicide metal-containing layer is formed of cobalt having a uniform resistivity, and the non-silicide metal-containing layer is substantially free from elements other than cobalt.
 15. The integrated circuit device of claim 10, wherein the source/drain silicide region and the metal silicide layer contact opposing surfaces of the metal nitride layer.
 16. The integrated circuit device of claim 10, wherein the metal nitride layer comprises a metal different from metals of the source/drain silicide region and the metal silicide layer.
 17. The integrated circuit device of claim 10, wherein the metal silicide layer has a gradient percentage of silicon.
 18. An integrated circuit device comprising: a transistor comprising: a semiconductor region; a gate stack overlying the semiconductor region; a source/drain region adjacent to the gate stack; and a contact plug electrically connecting to one of the gate stack and the source/drain region, wherein the contact plug comprises: a cobalt silicide layer; and a non-silicide cobalt-containing layer over the cobalt silicide layer.
 19. The integrated circuit device of claim 18 further comprising a metal nitride layer underlying and contacting the cobalt silicide layer.
 20. The integrated circuit device of claim 18, wherein the cobalt silicide layer has a gradient cobalt percentage. 